ESD protection for deep-submicron CMOS technology using gate-couple CMOS-trigger lateral SCR structure

A novel ESD protection circuit, which first combines the advantages of complementary low-voltage-trigger SCR devices and the gate-couple technique, is proposed to more effectively protect the thinner gate oxide of deep submicron CMOS ICs without adding an extra ESD-implant mask. Experimental results have verified its excellent ESD-protection capability.