Underlap channel UTBB MOSFETs for low—power analog/RF applications

In this work, we report on the significance of underlap channel architecture in Ultra Thin Body BOX (UTBB) fully—depleted (FD) SOI MOSFETs to improve analog/RF performance metrics. It is shown that at lower current levels and shorter gate lengths, underlap UTBB MOSFETs can achieve significant improvement ≫ 1.5 times in key analog/RF metrics over devices designed with conventional S/D architecture. Analog/RF figures of merit are analyzed in terms of spacer—to—straggle ratio (s/σ), a key parameter for the design of underlap devices. Results suggest that underlap S/D design with s/σ ratio of 3.3 is optimum to enhance analog/RF metrics at low current levels (≪ 60 μA/μm). The present work provides new viewpoints for realizing future low—power analog devices/circuits with underlap UTBB FETs.