Static and low frequency noise characterization of FinFET devices

A detailed electrical characterization of advanced triple-gate FinFETs focusing on mobility extraction at short gate length and narrow Fin effects is reported. Low temperature measurements in the range of 100 K-300 K and interface quality determination are also performed for better physical insights. In conclusion, the mobility is degraded at small gate length in sub 100 nm FinFETs using parameter extraction conducted at room temperature and low temperature; by proper extraction technique sidewall and top conductions have been separated, showing that sidewall mobility is about 25-30% degraded as compared to top surface conduction, likely resulting from Fin patterning-induced defects and/or crystal orientation difference; and trap density in high-k/MG stack is larger in pure SiO
₂
MOSFETs but with no further degradation at small Fin widths.