A design of high-performance multiplier for digital video transmission

A high performance design methodology is described for a multiplier to be used for digital video transmission. The key factor for such a multiplier is to operate at the speed of 30-100 MHz but with the precision of 8-10 bits, since it is intended for FIR filtering of digital video data. In terms of implementing an FIR filter with more than ten taps, the same number of multipliers are required to be integrated. Moreover, for the preloadability of coefficients to the filter, each coefficient can be treated as a constant during the filtering operation. Motivated by these requirements and functionalities, a novel multiplier architecture is described, which is to be synthesized with the use of a high level synthesis tool PARTHENON in conjunction with manually designed macroblocks. Design results of the multiplier are also shown.