A VLSI-oriented parallel FFT algorithm

Usually, parallel pipelined FFT processors are used to compute long FFTs due to high processing rate and easy implementation. The efficient VLSI implementation of each FFT processor at the pipelines is a critical problem to be considered. We propose a new parallel FFT algorithm that removes the complex multiplier between the two pipeline stages. The new algorithm also simplifies the address generation of twiddle factors and reduces the number of twiddle factors to a minimum. With the new algorithm, each FFT processor at the pipelines can be integrated easily onto a single chip.