A/D converter using Iterative Divide-by-Two Reference for CMOS image sensor

This paper proposes an ADC using Iterative Divide-by-Two Reference. Using and sharing a single voltage divider reduces silicon area for a column compared with the conventional SA-ADC. An offset-cancelled integrator and a capacitor error averaging method are implemented to decrease the impact of nonlinearities. The ADC is designed in 0.18-mum CMOS process and consumes 0.35-mW of power per ADC, and the active die area is 0.012-mm
²
.