Leakage optimization using transistor-level dual threshold voltage cell library

Recently, a transistor level dual-V
_th
technique has been proposed, where transistors within the same cell are allowed to have different V
_th
to form the so-call mixed V
_th
(MVT) cell. However, it is impractical to build a full MVT cell library and include it in the standard dual V
_th
design flow. To make this practical, current approach adds another design phase after technology mapping to replace high leakage cells with their low leakage MVT variants. We propose a method to seamlessly and effectively integrate transistor-level dual V
_th
technology into existing low power design flow. This paper reports our successful experience in applying this method to optimize leakage under timing constraints in an industrial design environment. For demonstration purpose, we build an MVT library based on only 15 cells in a standard library that contains 590 cells. On 11 ISCAS benchmarks and three industrial designs, this MVT library optimizes 27% of the design. Yet it gives an average of 9% and up to 25% leakage saving over the state-of-art gate level dual V
_th
design with a full size high V
_th
library.