An efficient Modified Booth multiplier architecture

We present the design of an efficient multiplication unit. This multiplier architecture is based on radix 4 booth multiplier. In order to improve his architecture, we have made 2 enhancements. The first is to modify the Wen-Chang's modified booth encoder (MBE) since it is the fastest scheme to generate a partial product. However, when implementing this MBE with the simplified sign extension (SSE) method, the multiplication's output is incorrect. The 2
^nd
part is to improve the delay in the 4:2 compressor circuit. The redesigned 4:2 compressor reduced the delay of the carry signal. This modification has been made by rearranging the Boolean equation of the carry signal. This architecture has been designed using Quartus II. The Gajski rule has been adopted in order to estimate the delay and size of the circuit. The total transistor count for this new multiplier is being a slightly bigger. This is due to the new MBE which is uses more transistor. However in performance speed, this efficiency multiplier is quite good. The propagation delay is reduced by about 2% - 7% from other designers.