A Low Kick Back Noise Latched Comparator for High Speed Folding and Interpolating ADC

This paper presents an improved latched comparator which is suitable for high speed folding and interpolation ADC. The proposed comparator minimizes the kick back noise. Dummy transistors are introduced in the switch circuit to suppress clock feedthrough. Transistors in common-gate arrangement are inserted to reduce kick back noise. Simulated result of the proposed circuit in a 0.18 um standard CMOS technology shows that, this comparator achieves low offset of 4 mV, reduces kick back noise to 0.5 mV, exhibits low power dissipation of 193 uW at 3.3 V supply at a very high speed operation of 250 MHz.