ASIC packaging challenges with high speed interfaces

Networking speed is exploding as demanded with technology advancements and industry chip technology is evolving with rapidly increasing serial link data rates with high link integration for higher aggregate bandwidth and shrinking chip area and interface dimensions of devices. However, a large development speed gap between chip technologies and package technologies places great packaging challenges for high speed link applications where package wireability is driven by high frequency performance requirements. This paper discusses packaging challenges of high speed link applications with cost-performance tradeoffs in the technology trend.