A 6-bit, 1.2-GS/s dual channel ADC in 0.13-μm CMOS for MB-OFDM UWB receivers

This paper presents a 6-bit, 1.2-GSample/s flash ADC for MB-OFDM UWB receivers fabricated in TSMC 0.13-mum CMOS 1P8M process. Using a dedicated track-and-hold amplifier (THA) at front, it can eliminate different paths skew between comparators and clock jitter degradation to the comparators. Moreover, the proposed converter is designed with averaging and interpolation technique so that the offset of the preamplifiers and comparators, and power consumption can be reduced. A reference generator generating reference voltage for preamplifiers array also has been included in this design. It can track the common mode voltage between THA and resistor ladder center tap. Operating at 1.2-GS/s both the I/Q channel ADC achieves an effective resolution bandwidth (ERBW) of 450-MHz, and greater than 5-bits effective number of bits (ENOB) at 350-MHz of input frequency. The peak DNL and INL are measured as 0.39-LSB and 1-LSB, respectively. A single channel ADC consumes about 84-mW including internal reference at 1.2-V supply. The test chip single channel occupies 1.45x0.78-mm
²
of active area.