Modeling the VTH fluctuations in nanoscale Floating Gate memories

Tight bits distribution is a must to fabricate multi-level Non-Volatile Memory (NVM) technology needed to reach a high degree of integration. On the contrary, the Non-Volatile cell shrink to nanoscale sizes produces a huge modulation in the device performances when atomistic scale fluctuations occur. The present work provides a new physically-based model allowing describing, through a simple analytical approach, the statistical V
_TH
spread for Floating Gate based NVM technologies with nanoscale dimensions.