Designs of the basic block reassembling Instruction Stream Buffer for X86 ISA

The potential performance of superscalar processors can be exploited only when processor is fed with sufficient instruction bandwidth. The front-end units, the Instruction Stream Buffer (ISB) and the fetcher, are the key elements for achieving this goal. Current ISBs cannot support instruction streaming beyond a basic block. In x86 processors, the split-line instruction problem worsens this situation. We proposed a basic blocks reassembling ISB in this paper. By cooperating with the proposed Line Weighted Branch Target Buffer (LWBTB), the ISB can predict advance branch information and reassemble cache lines. Front-End could fetch more valid instructions in a cycle by reassembling the original line containing instructions for the next basic block. Simulation results show that the cache line size over 64 bytes has a good chance to let two basic blocks in the reassembled instruction line and the fetch efficiency is about 90% as the fetch capacity is under 6.