Implementation of a configurable router for embedded network-on-chip support in FPGAs

This paper presents the architecture and implementation of a configurable router intended for embedded network-on-chip support within field-programmable gate arrays. The router supports five network topologies and utilizes a dual-crossbar arrangement to reduce resource utilization. The router has been implemented in an Altera Stratix chip and in a 0.18-mum standard-cell process. For the routing and switching logic, the dual-crossbar arrangement is more area-efficient than a full crossbar, averaging a reduction of 24% in FPGA logic and 22% in gates for custom implementation. The average operating frequency of the dual-crossbar design is 123 MHz in FPGA logic and 340 MHz for custom implementation. Custom NoC support in an FPGA would therefore have adequate performance relative to components implemented in fully-programmable logic.