FPGA Implementation of an Iterative Receiver for MIMO-OFDM Systems

Today iterative receivers have proved their efficiency in cancelling interference within the field of wireless communications. However their complexity is often seen as a brake for their use in real systems. In this paper an efficient iterative receiver real-time implementation for a 4 times 4 MIMO system is presented. An architecture of MMSE iterative receiver for MIMO-OFDM systems is proposed to limit latency and complexity due to iterative process: MMSE equalization implementation is realized using CORDIC operators; the scheduling between MIMO detection and channel decoding is optimized and specific interleaving functions are introduced to reduce latency and accelerate the convergence process. The implemented receiver is integrated in a real-time FPGA testbench and compared in terms of complexity and performance with a non iterative solution.