Broadband Active Balun Using Combined Cascode–Cascade Configuration

A new configuration is proposed for an active balun, which uses a cascode and cascade pair with the shared input transistor. It is designed in the IBM 8HP 130-nm BiCMOS process, which operates over a broad bandwidth up to 17 GHz where the imbalance of the differential output is less than 1.8 dB in amplitude and less then 10° in phase, over the input's dynamic range of $-{\hbox{25–5 dBm}}$, under the dc power consumption of 198.8 mW. The circuit contains no internal dc blocking capacitors so that the bandwidth's lower end frequency best extends as close to dc as possible. The circuit contains only one line inductor with the value of 0.2 nH, and the compacted layout is expected to fit in limited chip areas as small as 0.2 mm $\times$ 0.2 mm, which makes them well suited for built-in self-test applications, as well as general differential circuits requiring compact-sized broadband baluns.