55V Integrated Power and Non-Volatile Technology for Solid State Lighting Applications

This paper presents a process in which a 55 V-class of power devices is added to baseline 0.25 um 2.5 V/5 V/ 20 V CMOS technology by forming asymmetric extended-drain device structures in which an inverted well design concept is utilized to form an extended-drain dielectric region. The RsP-BVdS figure-of-merit is consistent with best-in-class (0.65 mOhm cm
²
/ 70 V NMOS, 1.60 mOhm cm
²
/ 70 V PMOS), and the voltage handling is drift-length scalable from 20 V to over 75 V. Three classes of non-volatile memory are modularly implemented in the process flow consisting of single- polysilicon hot-carrier programmed OTP, single polysilicon 2T FN-FN MTP, and double-polysilicon 2T EEPROM. The combination of high-performance integrated power devices with non-volatile memory results in cost-effective implementation of features necessary for solid-state lighting systems.