Local distribution of residual strain in 3-D stacked flip chips measured by strain sensor chips with 2-μm long piezoresistive gauges

Electronic products such as mobile phones and PCs have been miniaturized continuously and their functions have been improved drastically. So far, the electronic interconnection between a chip and a substrate has been wire bonding, but it has started to be changed to flip chip interconnection structures because signal delay clearly appears due to the increase of the resistance caused by the thinning of the wire. Area-arrayed tiny metallic bumps such as Cu or solder are applied to the flip chip structure and they are surrounded by insulating material (underfill) for assuring the reliability of the interconnection. Since the total thickness of the stacked structure is strictly limited for the mobile application, in particular, the thickness of a chip has been thinned to less than 50 μm to minimize the total thickness of the modules or packages.