Bandwidth efficient coded modulation and its implementation on FPGA

A method of bandwidth efficient coded modulation and its implementation on FPGA is presented. The proposed coding technique parses the input data into two blocks corresponding to ODD parity block and EVEN parity block, calculates and appends the vertical parity from the columns, and transmits the coded blocks across the channel. Horizontal parity bits from the rows are not calculated since they are ODD and EVEN corresponding to the respective blocks. This technique reduces the number of redundant bits and enhances bandwidth efficiency. Simulation results are presented to verify the concept. The method will be experimentally verified in the laboratory by implementing it on a field programmable gate array (FPGA).