Electrical Characteristics of Memory Devices With a High- $k$ $\hbox{HfO}_{2}$ Trapping Layer and Dual $\hbox{SiO}_{2}/\hbox{Si}_{3}\hbox{N}_{4}$ Tunneling Layer

A novel device structure with a high-k HfO
₂
charge storage layer and dual tunneling layer (DTL) (SiO
₂
/Si
₃
N
₄
) is presented in this paper. Combining advantages of the high trapping efficiency of high-k materials and enhanced charge injection from the substrate through the DTL, the device achieves a fast program/erase speed and a large memory window. The device demonstrates excellent retention due to its physically thick DTL and also improved endurance without any increase of programming V
_th
throughout the cyclic test as compared with SONOS Flash memory devices using an Si
₃
N
₄
trapping layer.