The Localized-SOI MOSFET as a Candidate for Analog/RF Applications

In this paper, the characteristics of a localized-SOI (L-SOI) MOSFET are investigated for analog/RF applications. In the L-SOI device, the source/drain regions are quasi-surrounded by L-type oxide layers to reduce junction capacitance and avoid source/drain punchthrough, while the channel is directly connected with the substrate to alleviate the self-heating effect. Such structures can combine the advantages of both bulk and SOI MOSFETs and avoid their issues. Due to the unique structure of this novel device, the L-SOI MOSFET can exhibit excellent analog/RF behaviors. Higher
g

_m
/
I

_ds
ratio and intrinsic gain (
g

_m
/
g

_ds
)can be received compared with the conventional SOI structure, particularly at low gate bias. Higher and , which are due to higher
g

_m
and reduced gate capacitance, can be observed in the L-SOI MOSFET. In addition, better noise performance can be achieved resulting from reduced lattice temperature and improved
g

_m
. Thus, the L-SOI MOSFET can be considered as one of the potential candidates for analog/RF applications.