A high-fidelity decimator chip for the measurement of sigma-delta modulator performance

This paper reports on results from the algorithmic design and simulation of a two-path polyphase decimation filter with 24-bit accuracy over the frequency range from dc to 15.2 kHz. The filter is suited for very high precision data conversion and measurement applications. The device reported in this paper has been designed for use with a fourth-order, single-loop, /spl Sigma//spl Delta/ modulator running at 4096 kHz. Results of floating and fixed-point simulations, architectural design, comparative bit-level simulations and silicon implementation of the decimator are also reported, together with a sample baseband measurement of a fourth-order modulator.<
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