Experimental Results for Parasitic Coupling and Attenuation of Coplanar Waveguides on High Resistivity Silicon

In high density MMIC circuits, parasitic coupling becomes a critical design consideration and adequate spacing between closely placed circuits is necessary to avoid unwanted interaction. In this paper, a measurement-based estimate for minimum spacing required between CPW lines fabricated on silicon is presented. It is shown that parasitic coupling between CPW lines can be reduced by a factor of 10dB if the silicon substrate around the ground plane is etched. Measured results for attenuation are also presented for CPW lines fabricated on a 425μm thick Si substrate using 1μm layers of either high temperature oxide (HTO) or evaporated SiO. It is shown that the loss on SiO is 3× lower when compared to SiO2 - based configurations.