Linear IC parasitic element simulation methodology

Linear IC design requires an intimate understanding of how the physical circuit realization affects the electrical performance of the circuit. An overview of parasitic elements of consequence in linear IC design is followed by a straightforward methodology to include these physical considerations into the electrical schematic such that the circuit simulations will take these elements into account. A design example including normal simulation, parasitic simulation, and bench test results is presented. This methodology allows the designer to more completely describe the circuit and improve the chances for first time design success.<
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