55-mW 1.2-V 12-bit 100-MSPS Pipeline ADCs for Wireless Receivers

For wireless receivers, low-power 1.2-V 12-bit 100-MSPS pipeline ADCs are fabricated in 90-nm CMOS technology. To achieve low-power dissipation at 1.2 V without the degradation of SNR, the configuration of 2.5bit/stage is employed with an I/Q amplifier sharing technique. Furthermore, single-stage common-source amplifiers are used in a sample-and-hold (S/H) circuit and a 1st multiplying digital-to-analog converter (MDAC). The common-source amplifier with two-stage transimpedance gain-boosting amplifiers realizes more than 90 dB. The measured SNR of the 100-MSPS ADC is 66.7 dB at 1.2-V supply. Under the condition, each ADC dissipates only 55 mW