Super-self-aligned back-gate/double-gate planar transistors with thick source/drain and thin silicon channel

This work presents a reproducible super-self-aligned approach to the fabrication of back-gate/double-gate transistors with thin silicon channels and thick source/drain poly-silicon access regions. Both n-channel and p-channel devices exhibit high drive currents, strong back-gate control and high effective carrier mobility. The unique attributes of our approach include a very effective control of 1) the silicon channel thickness, 2) thick source/drain formation, 3) solidstate diffused junctions from the doped poly-silicon source/drain into the un-doped Si channel, and 4) super-self-alignment between the back gate and the front gate with additional buried interconnections among devices. This approach eliminates the need of epitaxial growth of silicon and irreproducibility of wet etching to form back gate under cut of previous studies.