Automated Generation of Hardware Accelerators with Direct Memory Access from ANSI/ISO Standard C Functions

Methodologies for synthesis of stand-alone hardware modules from C/C++ based languages have been gaining adoption for embedded system design, as an essential means to stay ahead of increasing performance, complexity, and time-to-market demands. However, using C to generate stand-alone blocks does not allow for truly seamless unification of embedded software and hardware development flows. This paper describes a methodology for generating hardware accelerator modules that are tightly coupled with a soft RISC CPU, its tool chain, and its memory system. This coupling allows for several significant advancements: (1) a unified development environment with true pushbutton switching between original software and hardware-accelerated implementations, (2) direct access to memory from the accelerator module, (3) full support for pointers and arrays, and (4) latency-aware pipelining of memory transactions. We also present results of our implementation, the C2H compiler. Eight user test cases on common embedded applications show speedup factors of 13x-73x achieved in less than a few days