Systolic design of a new finite field division/inverse algorithm

A systolic architecture of a newly developed algorithm for performing division and inversion over GF(2/sup m/) has been successfully realized. It is novel in that the normal inverse/multiplication steps are integrated and the generator polynomial is selectable. The new design with its inherent regularity offers an expandable, fully pipelined high performance circuit, that is very suitable to a VLSI implementation. A GF(2/sup 8/) divider has been successfully implemented under the EUROCHIP program.<
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