General algorithms for a simplified addition of 2's complement numbers

Two algorithms for both a simplified carry save and carry ripple addition of 2's complement numbers are presented. The algorithms form the partial products so that they exclusively have positive coefficients which eliminates the need for the common sign bit extension. This results in a reduction of circuit area by up to six full adders per row of adders when partial products are added in an N/2 or Wallace tree. Furthermore, the capacitive load of the intermediate sum and carry sign bit signals decreases by up to a factor of seven which leads to an appropriate reduction of delay. Although the algorithms are derived for multipliers they can always be applied to appropriate adder circuits.<
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