A 0.4-/spl mu/m/sup 2/ self-aligned contactless memory cell technology suitable for 256-Mbit flash memories

This paper describes advanced self-aligned contactless memory-cell technology with sector erase and programming operations for a single power supply 256-Mbit flash memory. Using new self-aligned field-isolation technology and a deep punch-through stopper while minimizing the thermal budget of memory-cell fabrication process, 0.40-/spl mu/m/sup 2/ cells based on 0.25-/spl mu/m CMOS processes are fabricated.<
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