Mapping VHDL descriptions of digital systems to FPGAs

FPGAs provide a ready means of realising medium to large digital systems in a cost effective manner. As the complexity of these components increases there is a need to provide suitable high-level tools. All vendors offer suites of design tools for their products: these could be interfaces to standard schematic capture packages so that netlists can be provided. These netlists are then processed by the device-specific layout and interconnect tools to produce the final design. Tn addition to this route, some vendors offer editors which enable individual cells to be personalized, The trend in system design is to use high-level descriptions as much as possible, so that designs are to a large extent self-documenting. When high-level hardware description languages are employed then there are tools available which map or compile the design to the target hardware. These tools are in their infancy and hence they tend to deal only with subsets of the languages. The tools which this paper describes are concerned with automating the migration of a design created in VHDL to programmable logic.<
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