Parallel implementation of a 4*4-bit multiplier using a modified Booth's algorithm

The design of a 4*4-bit multiplier using the modified Booth's algorithm in 2- mu m NMOS technology is discussed. The main features of this chip are its 62.5-MHz operating frequency and 31.5-mW power dissipation. The chip occupies an area of 1.37 mm/sup 2/. A novel adder-cum-subtractor circuit was designed to realize the arithmetic processing part.<
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