The effect of substrate bias on hot-carrier damage in NMOS devices

Hot-carrier stressing carried out as a function of substrate voltage on 2- mu m NMOS devices under bias conditions V/sub d/=8 V and V/sub g/=5.5 V is discussed. The time power-law dependence of stressing changes as a function of substrate bias (V/sub b/), having a power-law gradient of 0.5 for V/sub b/=0 V and 0.3 for V/sub b/=-9 V. Investigation of the type of damage resulting from stressing shows that at V/sub b/=0 V, interface state generation results, while at V/sub b/=-9 V, the damage is mostly by charge trapping. Measurements of the gate current under these two substrate bias conditions show that the gate electron current increases by over two orders of magnitude upon application of a strong back bias. It is suggested that the electron trapping arises from this enhanced gate electron current under large substrate voltage conditions.<
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