Optimizing C compiler for the TRON architecture

A discussion is given on the development and effects of an optimizing C compiler for the GMICRO F32 series of 32 bit microprocessors which are available for the TRON (the real time operating system nucleus) architecture. Compiler optimizations for the TRON architecture, or the CISC (complex instruction set computer) architecture with its distinct features, were achieved through a clarification of the conflict (trade-off) between the increased execution rate and the reduced object size to produce an optimizing C compiler. In particular, the application of the '1:2 rule' to the execution rate and the object size achieved the compiler optimization for this CISC architecture. That this optimizing C compiler will accomplish the objective of applying many types of application programs written in C language to the TRON architecture.<
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