Efficient scheduling of fine grain parallelism in loops

Anti-dependencies are a major cause of bottleneck in software pipelining. Anti-dependencies can be removed in software by code duplication as in the technique of modulo variable expansion. However, it is possible to eliminate anti-dependencies in hardware. So far, two such VLIW architectures have been proposed: polycyclic and URPR-1 architectures. These architectures also introduce attractive solutions for the memory contention problem in general. We, on the other hand, propose a more cost-effective architecture for the same purpose: SRFA. SRFA is based on "shifting register files".<
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