Interconnect testing for bus-structured systems

This paper considers the problem of generating test vectors for interconnect testing within a boundary-scan environment. Provision is made for both detection and diagnosis of single and multiple bridging faults and stuck faults on driver and bus lines. The procedures developed cater for all combinations of structures within a board, and allow for the special problems of CMOS elements. The test set developed is shorter than those generated using algorithms previously reported in the literature.<
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