Semantics and synthesis of signals in behavioral VHDL

Signals are a fundamental part of VHSIC hardware description language (VHDL) behavioral descriptions. Synthesis tools often inadequately address synthesis of global signals. The research presented eases the restrictions placed by existing synthesis systems on the VHDL shows that can be used to specify designs. In order to obtain functionally equivalent hardware from VHDL descriptions, it is essential to understand the semantics of VHDL constructs, especially for signals driven by several processes. The authors have introduced a conceptual hardware representation to explain the semantics of signals, ports, and resolution functions. Procedures to synthesize hardware for such constructs are given.<
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