Gate arrays simplify translation between high speed logic families

TTL dominates todays I/O specifications. However, ECL logic provides increased bandwidth and low noise in a transmission line environment. High performance designs increasingly need to combine ECL and TTL interfaces. This paper presents a flexible approach to mixed signal level translations (ECL/PECL and TTL) utilizing a single I/O cell on a family of ECL gate arrays. The incorporation of Schottky diodes within the bipolar process provides high performance on/off chip logic translations to complement the 2.6 Gb/s ECL I/O interface capability. Versatile high speed system applications are illustrated and described.<
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