Routability design for sea-of-cells

The routability design of a core cell for three layer sea-of-cells is discussed. A formula to estimate both horizontal and vertical routing tracks in a core cell is derived. The estimation is based on average pin counts per base cell, and the number of rows and columns of base cells in an array. The formula has been applied to a series of bipolar and BiCMOS array families. The accuracy of the prediction has been verified by both experiments and actual chip production.<
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