Optimization of cyclic redundancy-check codes with 24 and 32 parity bits

The method developed by T. Fujiwara et al. (1985) for efficiently computing the minimum distance of shortened Hamming codes using the weight distribution of their dual codes is extended to treat arbitrary shortened cyclic codes. Using this method implemented on a high-speed special-purpose processor, several classes of cyclic redundancy-check (CRC) codes with 24 and 32 parity bits are investigated. The CRC codes of each class are known to have the same minimum distance d_min.L in a certain range L of block lengths n, and within each class that CRC code has been determined the minimum distance of which exceeds d_min.L up to the largest block length. The d_min profiles of the resulting codes are presented and compared with the d_min profiles of recent suggestions of P. Merkey and E. C. Posner (1984), as well as with the d_min profile of the widely used 32 parity-bit standard code recommended in IEEE-802