A 10 b 50 MS/s pipelined ADC

Most multistep analog-to-digital converter (ADC) architectures presented thus far suffer from poor linearity caused by the sample and hold as well as the internal digital-to-analog converter (DAC). Furthermore, the gain-matching between coarse and fine ADC gives rise to nonmonotonicity. A fully differential two-step ADC is described which presents solutions for sample and hold, the DAC, the gain-matching between coarse and fine high performance with low power consumption and small chip area.<
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