Flexible block-multiplier generation

A multiplier structure is described which leads to a very efficient implementation in a module generator environment. The structure, a block-multiplier, features a wide range of area-time tradeoffs maintaining efficiency. The structure makes it possible to implement a fully serial or a fully parallel multiplier and many combinations in between. A new concept for the carry-hold circuitry plays a key role. The theoretically derived formulas which describe the relations between the area, timing, and bitwidth of this multiplier structure are verified by a large number of experiments.<
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