Efficient microcode arrangement and controller synthesis for application specific integrated circuits

The authors present a controller synthesizer for application-specific multi-function-unit processors. They describe the data path, control path, and timing scheme of the design. They discuss the optimization problems for this architecture, including the translation of a controller-independent schedule into a microprogram to fit the timing scheme and the address assignment of micro-words. They verify the designs using a function simulator and a timing simulator. The synthesized results are proved to be correct by simulation, and a design with 22 ns for each phase, which corresponds to 23 MHz, has been obtained.<
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