A million transistor systolic array graphics engine

A description is given of a million transistor systolic array graphics engine (SAGE) that can render a horizontal 3-D span in every clock cycle at the rate of 25 million spans/s, independent of the pixel length of the span. For the average span length in the 10-32 pixel range, this translates into 250-800 million pixels/s. Assuming that the front end of the system can generate a span in every clock cycle, then in the best case SAGE polygon performance is 25,000,000 polygons/s for 100 pixel polygons and drops down to 750000 polygons/s as the average area of the polygons increases to 1000 pixels. For example, a system using the SAGE chip has the potential to interactively display the motion and time behavior of a 20000 polygon scene at a rate of 30 frames/s. In the extreme case where all spans are 1024 pixels long, SAGE operates at a peak parallel pixel-processing rate of 25000 million pixels/s.<
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