A Program for Device Model Parameter Extraction from Gate Capacitance and Current of Ultrathin$hboxSiO_2$and High-$kappa$Gate Stacks

A modeling tool is demonstrated for fast and automatic gate dielectric characterization and parameter extraction for the 45-nm CMOS technology node and beyond. The model incorporates a nonlinear least squares fitting program with the ability to extract nanometer-scale equivalent oxide thicknesses (EOTs) SiO
₂
and high-dielectric-constant (high-kappa) gate dielectrics from experimental gate capacitance (C
_g
-V
_g
) and gate leakage current (I
_g
-V
_g
) with high accuracy and efficiency. A modified Levenberg-Marquardt algorithm was used as the optimization approach. Improvements were made to reduce the chances of becoming stuck in local minima. A previously reported computationally efficient and accurate physically based compact model of self-consistent C
_g
-V
_g
and I
_g
-V
_g
model for both ultrathin SiO
₂
and high-kappa gate stacks of EOT down to ~ 0.5 nm is used as the basis for translating experimental C
_g
-V
_g
and I
_g
-V
_g
data to material and device parameters. In just a few seconds, for single and double layer gate dielectrics, device parameters such as EOTs, surface substrate doping concentrations, flatband voltages, and polysilicon doping concentrations (if applicable) can be extracted from measured gate capacitance data, and parameters such as physical thickness, band offsets, dielectric constants, and tunneling masses for the gate dielectrics can be extracted from measured gate current data. It was found that significant correlation exists between the effects of certain combinations of model parameters, especially for gate tunneling current. Thus, in this program, parameters can be fixed selectively for those already obtained with high confidence from other measurements. Box constraints can also be imposed, at the price of somewhat longer extraction time (up to ~ 1-7 min), for parameters to be optimized to improve the possibility of finding the correct parameters