A Combinatorial Solution to the Reliability of Interwoven Redundant Logic Networks

A combinatorial procedure is given to calculate the reliability of an interwoven redundant logic network to any desired degree of accuracy. The procedure consists of enumerating combinations of gate failure which are tolerated by the redundant network, and is explained with reference to a quadded logic network. Since the exact reliability calculation might be too time consuming for large networks, a formula is given for a lower bound which can be used in conjunction with the exact method to give a very accurate reliability figure with a comparatively small computation time.