Novel memory organization and circuit designs for efficient data access in applications of 3D graphics and multimedia coding

Memory has become one of the critical components in many applications. This paper presents new designs of SRAM memory circuit and architectures for applications in 3D graphics, JPEG2000, and multimedia codec. In the 3D graphics pipeline, the memory initialization is realized by modifying the circuits in the SRAM decoder and storage cell. In the bit-plane coder (BPC) of JPEG2000, we propose a new 3D memory architecture design and the corresponding circuit designs for efficient data access in processing the stripe-based bit planes. The 3D memory design can be also applied to the design of parallel-in-parallel-out transpose memory that is frequently encountered in the design of 2D DCT in JPEG and MPEG codec. We also develop a memory generator to allow for easy generation of the application-specific memory units of various sizes to be embedded in conventional cell-based design flow.