Capacity-Approaching LDPC Codes with Low Error Floors for High-Speed Digital Communications

This paper discusses the design of capacity-approaching irregular low density parity check (LDPC) codes constructed from circulant permutation matrices with low error floors. The experimental results indicate that the performance in the waterfall region of the error curve can be improved by increasing the maximum column degree or by decreasing the fraction of columns with maximum degree in the parity check matrix. To delay the onset of the error floor, several techniques in code constructions are proposed to optimize both the degree distributions and the cycle structures of irregular codes. Having encoder architectures supporting throughputs in the Gbits/s region, the proposed codes are suitable for high-speed applications of various digital communications