A new on-chip ESD protection circuit with dual parasitic SCR structures for CMOS VLSI

A novel CMOS on-chip ESD (electrostatic discharge) protection circuit which consists of dual parasitic SCR structure is proposed. Experimental results show that it can successfully provide for negative and positive ESD protection with failure thresholds greater than +or-1 kV and +or-10 kV in machine-mode (MM) and human-body-mode (HBM) testing, respectively. Moreover, low triggering voltages in both SCRs can be readily achieved without involving device or junction breakdown.<
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