A 60-MHz 64-tap echo canceller/decision-feedback equalizer in 1.2- mu m CMOS for 2B1Q high bit-rate digital subscriber line transceivers

A 60-MHz 64-tap adaptive FIR filter chip has been fabricated in 1.2- mu m CMOS which can implement either an echo canceller or decision-feedback equalizer for 2B1Q high bit-rate digital subscriber line (HDSL) transceivers. The 4.3-mm*4.3-mm, 30000-transistor chip is a complete self-contained adaptive filter which incorporates the LMS algorithm for coefficient updating. The device can be cascaded to implement very long filter lengths which are often required in high-bit-rate transceivers. At a 60-MHz clock rate the echo canceller/decision feedback equalizer chip can accommodate symbol rates in excess of 800 kbaud.<
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